Silicon Labs /SiM3_NRND /SIM3U166_B /PBHD_4 /PBFSEL

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Interpret as PBFSEL

PB3SEL=GPIO, PB2SEL=GPIO, PB0SEL=GPIO, PB1SEL=GPIO, PB5SEL=GPIO, PB4SEL=GPIO

Description

Function Select

Fields

PB0SEL	Port Bank n.0 Function Select. 0 (GPIO): Pin configured for GPIO. 1 (PMLS): Pin configured for Port Mapped Level Shift. 2 (EPCA0): Pin configured for EPCA0 output. 3 (RESERVED): Reserved.
PB1SEL	Port Bank n.1 Function Select. 0 (GPIO): Pin configured for GPIO. 1 (PMLS): Pin configured for Port Mapped Level Shift. 2 (EPCA0): Pin configured for EPCA0 output. 3 (RESERVED): Reserved.
PB2SEL	Port Bank n.2 Function Select. 0 (GPIO): Pin configured for GPIO. 1 (PMLS): Pin configured for Port Mapped Level Shift. 2 (EPCA0): Pin configured for EPCA0 output. 3 (UART1): Pin configured for UART1 TX.
PB3SEL	Port Bank n.3 Function Select. 0 (GPIO): Pin configured for GPIO. 1 (PMLS): Pin configured for Port Mapped Level Shift. 2 (EPCA0): Pin configured for EPCA0 output. 3 (UART1): Pin configured for UART1 RX.
PB4SEL	Port Bank n.4 Function Select. 0 (GPIO): Pin configured for GPIO. 1 (PMLS): Pin configured for Port Mapped Level Shift. 2 (EPCA0): Pin configured for EPCA0 output. 3 (UART1): Pin configured for UART1 RTS.
PB5SEL	Port Bank n.5 Function Select. 0 (GPIO): Pin configured for GPIO. 1 (PMLS): Pin configured for Port Mapped Level Shift. 2 (EPCA0): Pin configured for EPCA0 output. 3 (UART1): Pin configured for UART1 CTS. 4 (LPTIMER0): Pin configured for LPTIMER0 toggle output.

Links

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